The present invention relates to the manufacture of objects. More particularly, the invention provides a technique including a method and device for cleaving a substrate in the fabrication of a multi-layered substrate for semiconductor integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems (xe2x80x9cMEMSxe2x80x9d), sensors, actuators, solar cells, flat panel displays (e.g., LCD, AMLCD), biological and biomedical devices, and the like.
Many ways of fabricating substrates for the manufacture of integrated circuits have been proposed. In the early days, conventional integrated circuits were fabricated on xe2x80x9cbulkxe2x80x9d silicon wafers. These bulk silicon wafers were generally single crystal and formed using a process called Czochralski, which is known as CZ. The CZ process melts a batch of silicon metal in a crucible. A seed crystal is used as a starting material to pull a silicon ingot from the melt in the crucible. The ingot is then cut and polished to form the bulk silicon wafers.
Although bulk silicon wafers are widely used today, many such wafers have been replaced by other types. These other types of wafers include, among others, epitaxial silicon wafers, silicon-on-insulator wafers, and the like. High purity applications often require the use of epitaxial silicon wafers. These applications often produce lower yields on CZ wafers so such epitaxial silicon wafers are desirable. High purity applications include the manufacture of high density memory devices, high voltage devices, and microprocessor devices.
Some applications also use silicon on insulator wafers. These wafers generally include a silicon material layer, where devices are to be formed, overlying an insulating layer, commonly made of silicon dioxide, which overlies a bulk substrate material. Silicon on insulator wafers, which are known as SOI wafers, are made using one of many techniques. A common technique for making such wafer is xe2x80x9cseparation by ion implantation of oxygen,xe2x80x9d also termed as SIMOX. These SIMOX wafers are often made by implanting high doses of oxygen impurities into a silicon substrate, where the oxygen is later annealed to create an insulating layer underlying a surface of the silicon substrate. An active device layer is defined overlying such insulating layer. SIMOX wafers, however, have numerous limitations. For example, SIMOX wafers are often difficult to make in an efficient manner, since the high doses often require a long implantation time. Implantation is generally an expensive operation in the manufacture of wafers. Additionally, implantation of oxygen often causes damage to the device layer. Such damage can influence the operation and reliability of integrated circuit devices that are fabricated onto the device layer.
Accordingly, other ways of developing SOI wafers have been proposed. One such way is a xe2x80x9cblisteringxe2x80x9d method for film separation known as Smart Cut(trademark). Such blistering technique is described in detail in U.S. Pat. No. 5,374,564, in the name of Bruel (xe2x80x9cBruel ""564xe2x80x9d). This thermal blistering technique for manufacturing SOI wafers has many limitations. For high volume production, the high doses of hydrogen often requires the use of many ion implanters, which are expensive and difficult to maintain. Additionally, thermal blistering often creates rough surface finishes, which can produce worthless scrap product. European Application No. EP 0807970A1 (xe2x80x9cAspar ""970xe2x80x9d), which is also in the name of Aspar, suggests an improved method to the Bruel ""564 patent of forming SOI wafers. Aspar ""970 suggests a method of mechanically separating a layer having microcavities or microbubbles. Although the Aspar ""970 suggests that the doses are generally lower than a minimum causing surface blistering, the doses of hydrogen should still be sufficiently high to allow microcavity and microbubble coalescence through a subsequent heat treatment process. Such thermal treatment process would often require a high temperature, which would lead to an exceedingly rough and imprecise fracture morphology along the microcavity plane. Accordingly, the Aspar ""970 also requires high temperatures, which are generally undesirable and lead to excessive surface roughness characteristics.
Still another variation is described in U.S. Pat. No. 5,882,987, which is assigned to International Business Machines Corporation, and in the name of Srikrishnan, Kris V (xe2x80x9cSrikrishnanxe2x80x9d). Srikrishnan suggests an improvement to the blistering technique taught by the Bruel ""564 patent. Here, Srikrishnan suggests an etch-stop layer within a device layer to be released. Additionally, Srikrishnan suggests implanting a large dose of hydrogen to allow separation using the aforementioned xe2x80x9cblisteringxe2x80x9d process to separate the film at a location away from the etch-stop layer, thereby resulting in a structure characterized by the device layer covered by the etch-stop layer and a top surface layer and then selectively removing both layers. This process, which may be advantageous by reducing or eliminating the need for a chemical-mechanical polishing (CMP) step, still generally requires the use of the blistering process, high doses of hydrogen or rare gas ion implantation, and complicated chemical removals.
Yet another method for forming SOI wafers has been described in U.S. Pat. No. 5,854,123, which is assigned to Canon Kabushiki Kaisha, and in the names of Sato, et al (xe2x80x9cSatoxe2x80x9d). The Sato patent suggests releasing an epitaxial layer, which has been formed on a porous silicon layer. The porous silicon layer is generally made to release the epitaxial layer by providing a high degree of etch selectivity between the epitaxial silicon layer and the porous silicon layer. Unfortunately, this technique is often complicated and expensive. Moreover, epitaxial growth on a porous layer can compromise the quality of the epitaxial film by the introduction of defects into it, which is very undesirable. Other limitations can also exist with such technique.
Accordingly, a pioneering technique made by a company called Silicon Genesis Corporation has been developed. Such technique relies upon a controlled cleaving process, which is known as CCP, to manufacture SOI wafers and other structures. The CCP technique produces improved films using a room temperature process to cleave films. The room temperature process is generally free from microbubbles or microcavities, which may lead to blisters and the like caused by the conventional process described in Bruel. Although overcoming many limitations in conventional techniques, CCP can still be improved.
From the above, it is seen that an improved method for manufacturing substrates is highly desirable.
According to the present invention, a technique including a method and device for manufacturing objects is provided. In an exemplary embodiment, the present invention provides a method for fabricating multilayered substrates from a cleaving process.
In a specific embodiment, the present invention provides a method of forming substrates, e.g., silicon, silicon germanium. The method includes providing a donor substrate; and forming a particle accumulation region at a selected depth in the donor substrate. In a preferred embodiment, the particle accumulation region is made by introducing defects by way of implantation techniques (e.g., silicon ions) into a plane along such region. The method includes diffusing a plurality of particles from a higher concentration region into the particle accumulation region to add stress to the particle accumulation region; and separating a thickness of material above the selected depth in the donor substrate. Separating frees the thickness of material above the selected depth.
In a further embodiment, the present invention provides a method of fabricating a film of material for a Smart Cut(trademark) process. Here, the Smart Cut process is described in U.S. Pat. No. 5,374,564, which is incorporated by reference here. The method includes providing a donor substrate; and introducing a plurality of first particles through a surface of the donor substrate to a first depth to define a particle accumulation region and a material region about the particle accumulation region. The method also includes introducing a plurality of second particles to a second depth of the donor substrate; and diffusing the second particles from the second depth to the particle accumulation region to add stress to the particle accumulation region. The diffusion is continued to cause a crystalline rearrangement effect and a pressure to cause a separation of the material region from the donor substrate at the particle accumulation region.
Numerous benefits are achieved over pre-existing techniques using the present invention. The present invention produces less implant damage than conventional techniques. Additionally, the invention can require lower overall implant dosages. Further, the invention takes advantage of lower cost equipment such as a diffusion furnace, rather than an expensive implanter. Depending upon the application, one or more of these advantages may exist.
The present invention achieves these benefits and others in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.